A fully-integrated single-chip receiver for an 860–960 MHz UHF RFID reader is designed in 0.18 µm CMOS technology. It is mainly composed of an RF front-end, a DC offset cancellation (DCOC) block, and an analogue baseband. The RF front-end consists of a double- mode low noise amplifier (LNA) and an I/Q mixer. The LNA can operate under two different modes, which correspond to the listen-before-talk (LBT) mode and the normal mode specified by UHF RFID protocols, respectively. The common-gate structure and the dynamic current injection technique are used for the mixer to achieve high linearity and low 1/f noise. The analogue baseband comprises a programmable gain amplifier (PGA) and a low-pass filter (LPF). The opamp-based PGA is composed of a fine gain stage with a gain step of 1 dB, and a coarse gain stage with three fixed gain, corresponding to 6 dB, 12 dB and 24 dB, respectively. The LPF is a fourth-order Butterworth active RC one, whose bandwidth can be adjusted between 480 kHz and 1.68 MHz. Simulation results show that the receiver achieves P1 dB of −2.1 dB in LBT mode and sensitivity of −88 dBm in normal mode, with power dissipation of 95.72 mW from a 1.8 V power supply.