paper 150203030418

A 10-bit 200 MS/s Pipelined analog to digital converter (ADC) is realized using operational amplifier (op-amp) and capacitor sharing. A novel loading-balanced architecture is proposed to equal the capacitor load of the two adjacent stages which sharing one amplifier and reduce the load capacitor. Low power consumption is achieved by using loading-balanced architecture. The ADC is implemented in TSMC 0.18 µm 1P6M CMOS process. The supply voltage is 1.8 V. The simulation results show 57.7 dB SNDR and 61.13 dB SFDR with a 98 MHz input operating at a 200 MS/s sampling rate. The area is 1.2 mm × 1.2 mm.

Citation

Wen Wei He, Dong Li, Qiao Meng, Linfeng Wang, and Yi Zhang, "High Speed Pipelined ADC Uses Loading-balanced Architecture," Proceedings of 2015 Photonics & Electromagnetics Research Symposium, Prague, July 6 - 9，Page(s)811-815

References

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