paper 150203024727

A 10 bit 100 MS/s successive approximation register (SAR) analog-to-digital con- verter (ADC) is realized in 90 nm CMOS process. With the proposed logic control scheme and novel switch-driving register (SDR), the proposed SAR ADC achieves high conversion rate, low power, leading to SNDR of 59 dB and SFDR of 72.6 dB at 100 MS/s with 49.7 MHz input. The figure-of-merit (FoM) is 39.1 fJ/conversion-rate at 100 MS/s with a power consumption of 2.87 mW.

Citation

Wen Wei He, Dong Li, Qiao Meng, Linfeng Wang, and Yi Zhang, "10 bit 100 MS/s SAR ADC with Reduced Loop Delay," Proceedings of 2015 Photonics & Electromagnetics Research Symposium, Prague, July 6 - 9，Page(s)807-810

References

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