A single channel 2 GSps, 8 bit folding and interpolation (F&I) analog-to-digital converter (ADC) designed in TSMC 90 nm CMOS technology was presented in this paper. The ADC utilized cascaded folding architecture, which incorporated an additional inter-stage sample- and-hold amplifier between the two stages of folding circuits to enhance the quantization time. A pipelined track-and-hold amplifier (THA) with bootstrapped switch was taken as the front-end THA to improve its performance. The foreground digital assisted calibration was also employed in this design to correct the error of zero-crossing point caused by the circuit offset, thus to improve the linearity of the ADC. Chip area of the whole ADC including pads is 930 µm × 930 µm. Post simulation results demonstrate that under a single supply of 1.2 Volts, the ADC consumes 210 mW. For the clock of 2 GHz, the signal to noise and distortion ratio (SNDR) is 45.93 dB for Nyquist input signal frequency.