PhotonIcs and Electromagnetics Research Symposium,
also known as Progress In Electromagnetics Research Symposium
PIERS Proceedings
Published: 2015-07-09
Low-complexity Design of an 8 x 8 Modulation Configurable K-best MIMO Detector
By
Proceedings of 2015 Photonics & Electromagnetics Research Symposium, Prague, July 6 - 9,Page(s)1453-1457
Abstract
In this paper, a low complexity 8 × 8 MIMO detector supporting QPSK, 16-QAM, and 64-QAM is presented. A breadth-first type known as distributed K-best (DKB) algorithm is applied in the design. Compared with the conventional √ K-best algorithm, the DKB reduces the number of visited nodes at each layer from K M to 2K − 1, where K and M are the quantity of candidates and constellation size, respectively. To further reduce power consumption, a shift multiplier which simply operates bits shifting and additions is proposed to replace the conventional multiplier. In addition, the proposed multi-stage circuit architecture only requires K clock cycles to find the best K candidates, and the sorting circuits for the conventional K-best can be avoided in our design. The proposed 8 × 8 MIMO detector has been implemented by a 90-nm CMOS technology with a core area of 0.99 × 0.99 mm2 . The average power consumption is about 17.2 mW at 74 MHz and 1 V supply voltage.
Citation
Syu-Siang Long, and Muh-Tian Shiue, "Low-complexity Design of an 8 x 8 Modulation Configurable K-best MIMO Detector," Proceedings of 2015 Photonics & Electromagnetics Research Symposium, Prague, July 6 - 9,Page(s)1453-1457
References

1. Guo, Z. and P. Nilsson, "Algorithm and implementation of the K-best sphere decoding for MIMO detection," IEEE Journal on Selected Areas in Communications, Vol. 24, No. 3, 491-503, March 2006.
doi:10.1109/jsac.2005.862402        Google Scholar

2. Wenk, M., M. Zellweger, A. Burg, N. Felber, and W. Fichtner, "K-best MIMO detection VLSI architectures achieving up to 424 Mbps," Proc. of ISCAS, 1151-1154, 2006.
doi:10.1109/iscas.2006.1692794        Google Scholar

3. Shabany, M. and P. G. Gulak, "Scalable VLSI architecture for K-best lattice decoders," Proc. of ISCAS, 940-943, May 2008.
doi:10.1109/iscas.2008.4541574        Google Scholar

4. Chen, S., T. Zhang, and Y. Xin, "Relaxed K-best MIMO signal detector design and VLSI implementation," IEEE Trans. on Very Large Scale Integr. (VLSI) System, Vol. 15, No. 3, 328-337, 2007.        Google Scholar

5. Shabany, M., K. Su, and P. G. Gulak, "A pipelined scalable high-throughput implementation of a near-ML K-best complex lattice decoder," Proc. of ICASSP, 3173-3176, March 2008.
doi:10.1109/icassp.2008.4518324        Google Scholar

6. Burg, A., M. Borgmann, M. Wenk, M. Zellweger, W. Fichtner, and H. Bolcskei, "VLSI implementation of MIMO detection using the sphere decoding algorithm," IEEE Journal of Solid-State Circuits, Vol. 40, No. 7, 1566-1577, July 2005.
doi:10.1109/jssc.2005.847505        Google Scholar

7. Shabany, M. and P. G. Gulak, "A 0.13 µm CMOS 655 Mb/s 4 × 4 64-QAM K-best MIMO detector," Proc. of IEEE Int. Solid-State Circuits Conf. (ISSCC), 256-257, 2009.        Google Scholar

8. Liao, C.-H., T.-P. Wang, and T.-D. Chiueh, "A 74.8 mW soft-output detector IC for 8 × 8 spatial-multiplexing MIMO communications," IEEE J. Solid-State Circuits, Vol. 45, No. 2, 411-421, 2010.        Google Scholar