This paper presents the design of a 30-GHz low phase noise LC-tank voltage control oscillator (VCO) and a high speed frequency divided-by-two module in a 90-nm CMOS technology. A single cross-coupled PMOS transistor pair with drain resistors is adopted to suppress the flicker noise up-conversion. To improve the linearity, two sets of varators with different DC biasing are implemented. The simulated tuning range of the VCO covers from 28.7 to 32.4 GHz in four tuning curves. The simulated output phase noise at offsets of 10 kHz, 100 kHz and 1 MHz are −50, −78, and −104 dBc/Hz, respectively. The power consumption of the VCO is 9 mW under a 1.2-V power supply. A current mode logic (CML) divided-by-two module is designed to operate at 28 to 40 GHz. The divider core draws 3.3 mA from a 1.2-V supply.